members >> yoo, hoyoung

PERSONAL DATA

photo
  • Yoo, Hoyoung
  • Date of Birth: December 30, 1984 (the solar calendar)
  • Place of Birth: Goeje, Korea
  • Hobbies: Swimming and Watching american dramas
  • E-mail:
  • Homepage:

EDUCATIONAL BACKGROUND

  • KAIST: Electrical Engineering Ph.D. (2012.2~)
  • KAIST: Electrical Engineering M.S. (2010.2~2012.2)
  • Yonsei University: Electrical and Electronic Engineering B.S (2003.3~2010.2)
  • Goeje High School (2000.3~2003.2)

INTERESTS

  • Design for Embedded Systems
  • VLSI for Advanced Error Correction Codes
  • VLSI for Speech Recognition

PAPERS

    INTERNATIONAL JOURNAL PAPERS

    1. Hoyoung Yoo and In-Cheol Park, "Efficient Pruning for Successive-Cancellation Decoding of Polar Codes,"IEEE Communications Letters, vol. 20, no. 12, pp. 2362-2365, Dec. 2016.
    2. Byeong Yong Kong, Hoyoung Yoo, and In-Cheol Park, "Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 63, no. 7, pp. 673-677, Jul. 2016.
    3. Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, "Low-Power Parallel Chien Search Architecture Using Two-Step Approach," IEEE Transactions on Circuits and Systems-II: Express Briefs, vol. 63, no. 3, pp. 269-273, Mar. 2016.
    4. Jihyuck Jo, Hoyoung Yoo, and In-Cheol Park, "Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24, no. 2, pp. 754-758, Feb. 2016.
    5. Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, "Efficient Parallel Architecture for Linear Feedback Shift Registers," IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 62, no. 11, pp. 1068-1072, Nov. 2015.
    6. Hoyoung Yoo and In-Cheol Park, "Partially Parallel Encoder Architecture for Long Polar Codes," IEEE Transactions on Circuits and Systems II:Express Briefs, vol. 62, no. 3, pp. 306-310, Mar. 2015.
    7. Youngjoo Lee, Hoyoung Yoo, Injae Yoo and In-Cheol Park, "High-throughput and Low-complexity BCH Decoding Architecture for Solid-state Drives," IEEE Transactions on Very Large Scale Integration Systems, vol. 22, no. 5, pp. 1183-1187, May, 2014.
    8. Hoyoung yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, "Area-Efficient Multi-Mode Encoding Architecture for Long BCH Codes," IEEE Transactions on Circuits and Systems II:Express Briefs, vol. 60, no. 12, pp. 872-876, Dec. 2013.
    9. Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo and In-Cheol Park, "A 2.74pJ/bit, 17.7Gb/s Iterative Concatenated-BCH Decoder in 65nm CMOS for MLC NAND Flash Memory," IEEE Journal of Solid-State Circuits, vol. 48, no. 10, pp. 2531-2540, Oct. 2013.
    10. Youngjoo Lee, Hoyoung Yoo and In-Cheol Park, "Low-Complexity Parallel Chien Search Structure using Two-Dimensional Optimization," IEEE Transactions on Circuits and Systems II:Express Briefs, vol. 58, no. 8, pp. 522-526, Aug. 2011.
    11. Yoo, H., Lee, Y. and Park, I.-C., "Area-Efficient Syndrome Calculation for Strong BCH Decoding," IEE Electronics Letters, vol. 47, no. 2, pp. 107-108, Jan. 2011.

    INTERNATIONAL CONFERENCE PAPERS

    1. Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, "7.3 Gb/s universal BCH Encoder and Decoder for SSD Controllers," 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014), Singapore, Jan. 2014, pp. 37-38.
    2. Youngjoo Lee, Hoyoung Yoo, and In-Cheol Park, "A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13um CMOS process," 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Yokohama, Japan, Jan. 2013, pp. 85-86.
    3. Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, "Low-latency area-efficient decoding architecture for shortened ReedSolomon codes," IEEE International SoC Design Conference 2012 (ISOCC 2012), Jeju, Korea, Nov. 2012
    4. Youngjoo Lee, Hoyoung Yoo, and In-Cheol Park, "Small-Area Parallel Syndrome Calculation for Strong BCH Decoding," IEEE International Conference on Acoustics, Speech, and Signal Processing 2012 (ICASSP 2012), Kyoto, Japan, Mar. 2012, pp. 1609-1612.
    5. Youngjoo Lee, Hoyoung Yoo, Injae Yoo, and In-Cheol Park, "6.4Gbps Multi-Threaded BCH Encoder and Decoder for Multi-Channel SSD Controllers," IEEE International Solid-State Circuits Conference 2012 (ISSCC 2012), San Francisco, CA, USA, Feb. 2012, pp. 426-427.

    DOMESTIC CONFERENCE PAPERS

    1. Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo and In-Cheol Park, "A 7.34Gb/s (70528, 65536) Concatenated-BCH Encoder Using Two-dimensional Encoding Scheme," IEEK Summer Conference 2013
    2. Jihyuck Jo, Hoyoung Yoo, Soyoung Cha and In-Cheol Park, "Optimization of Floating-Point Bit-width for MFCC Feature Extraction," IEEK Summer Conference 2013
    3. Dong Joon Yoon, Hoyoung Yoo, Jihyuck Jo, and In-Cheol Park, "Implementation of AT91SAM9XE (ARM926EJ-S) Processor Simulator Using QEMU," 2012 IEEK Summer Conference, Jeju, Korea, Jun. 2012
    4. Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, "Comparison Between BCH and RS Decoders for High Performance Solid-State Drive," 2012 IEEK Summer Conference, Jeju, Korea, Jun. 2012
    5. Hoyoung Yoo, Youngjoo Lee and In-Cheol Park, "Implementation of Generator for Various Area-efficient High-performance Reed-Solomon Decoders," IEEK Fall Conference, Daejeon, Korea, Nov. 2011

CHIP DESIGN CONTESTS

  1. Hoyoung Yoo, Jihyuck Jo, and In-Cheol Park, "Efficient 32-bit real-time embedded platform for IoT systems," IEEE International SoC Design Conference 2014 (ISOCC 2014) Chip Design Contest, Jeju, Korea, Nov. 2014.
  2. Hoyoung Yoo, Youngjoo Lee, and In-Cheol Park, "7.3Gb/s universal BCH encoder for SSD controllers," IEEE International SoC Design Conference 2013 (ISOCC 2013) Chip Design Contest, Busan, Korea, Nov. 2013.
  3. Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, "Energy-efficient high-throughput iterative concatenated-BCH decoder for MLC flash memory," IEEE International SoC Design Conference 2013 (ISOCC 2013) Chip Design Contest, Busan, Korea, Nov. 2013.
  4. Youngjoo Lee, Hoyoung Yoo, Injae Yoo, and In-Cheol Park, "A 6Gbps SSD Controller using Low-complexity and Time-interleaved BCH Encoder/Decoder," IEEE Internal SoC Design Conference (ISOCC 2011) Chip Design Contest, Jeju, Korea, Nov. 2011.

PATENTS

  1. Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, "Concatenated BCH decoder and concatenated BCH decoding method," Korea 10-1512361
  2. Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo and In-Cheol Park, "Concatenated BCH encoding circuit, storage device and storage systme including the same," Korea 10-1433672
  3. Youngjoo Lee, Hoyoung Yoo, Injae Yoo and In-Cheol Park, "Multi-threaded BCH encoder, BCH decoder, storage device and storage system," Korea 10-1307792
  4. Youngjoo Lee, Hoyoung Yoo, and In-Cheol Park, "BCH decoder, memory system having the same and decoding method," Korea 10-1267958
  5. Youngjoo Lee, Hoyoung Yoo, and In-Cheol Park, "RS decoder, memory system having the same and decoding method," Korea 10-1226439
  6. Hoyoung Yoo, Youngjoo Lee and In-Cheol Park, "BCH decoder, memory system having the same and BCH decoding method," Korea 10-1190522
  7. Youngjoo Lee, Hoyoung Yoo and In-Cheol Park, "BCH decoder, memory system having the same and BCH decoding method," Korea 10-1154923
  8. Youngjoo Lee, Hoyoung Yoo and In-Cheol Park, "BCH decoder, memory system having the same and BCH decoding method," Korea 10-1126359

AWARDS

  1. Excellence in Research, KAIST EE, 2013-2015
    - Research Excellence Award
  2. Qualcomm Innovation Award, 2015
    - Hoyoung Yoo, Jihyuck Jo, and In-Cheol Park, "Energy-Efficient VLSI Architecture for HMM-based Isolated Word Recognition"
  3. Altera Design Contest, 2014
    - The First place
    - Hoyoung Yoo, Jihyuck Jo, and In-Cheol Park, "Speech Recognition for Automobile Systems"
  4. IEEE International SoC Design Conference 2014 (ISOCC 2014)
    - Chip Design Contest Best Demo Award
    - Hoyoung Yoo, Jihyuck Jo, and In-Cheol Park, "Efficient 32-bit real-time embedded platform for IoT systems"
  5. IEEE International SoC Design Conference 2013 (ISOCC 2013)
    - IEEE SSCS Seoul Chapter Best Demo Award
    - Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, and In-Cheol Park, "Energy-efficient high-throughput iterative concatenated-BCH decoder for MLC flash memory"
  6. Kim Choong-Ki Award, KAIST EE, 2013
    - Top 3 Research Excellence Award
  7. Global Ph.D. Fellowship, 2012
    - 2012.02 ~ 2015. 01
    - National Research Foundation of Korea
  8. Korean Intellectual Property Office (KIPO) IP Design Contest, 2011
    - Special Award
    - Youngjoo Lee, Hoyoung Yoo and Injae Yoo, "오류에 강인한 다채널 대용량 MLC SSD 컨트롤러의 설계"

EXPERIENCE

  • English Intensive Program
    - 2008.3 ~ 2009.1
    - Vancouver, Canada
  • Qualcomm IT Tour - Visiting student
    - 2009 Summer
    - Qualcomm Headquaters - R&D center, Sandiego

 

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