Deep-learning specific instruction-set processor

Incremental convolution increases data-reuse

Master-servant ISA maximizes computation speed

1D and 2D chain structure achieves higher scalability

"DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks"

Energy-efficient computer arithmetic

Weight quantiztion for multiplier-less operations

Low hardware complexity and power consumption

"Retrain-less Weight Quantization for Multiplier-less Convolutional Neural Networks"

High-performance object detection system

RISC processor controls the NPU and handles miscellaneous tasks

Two dedicated convolution accelerator: band and pointwise processor

Task manager is respensible for balancing the workload between RISC processor and NPU to improve the overall performance

Detecting system is implemented on Terasic DE4 board

"Real-Time SSDLite Object Detection on FPGA"

Processing in memory

A general-purpose CNN instruction set architecture (ISA) in memory for inference

High bandwidth and throughput due to the in-memory and row-wise processing

Compatible with the existing memory interfaces

On-chip neural-network processor (ONP) can be embedded into a commercial memory